MADISON, Wis. — Semiconductor engineers are already hearing AI’s footsteps as it encroaches on their design work.
Consider the vast amount of design data and variability required of chip designers, especially when developing a variety of chips with different power, temperature and performance specs. Complex IC designs might well be one of the logical areas to apply machine learning.
At least one EDA software company is making headway with home-grown machine-learning algorithms — calling it “machine learning for engineering” and applying it to variation-aware design and characterization software.
That company is Solido Design Automation, a privately-held EDA software vendor founded in 2005 in Saskatoon, Canada.
Solido has just become the first vendor to make commercially available its machine-learning algorithms to semiconductor customers, by launching Machine Learning (ML) Labs. Solido’s plan is to “collaboratively work with semiconductor companies to develop new ML-based EDA products,” according to the company.
President and CEO Amit Gupta told us, “We’d like to cast a wider net,” to work with more customers to explore, select and apply best ML technologies to solve specific problems.
12 years in Machine Learning
Solido is neither neophyte nor imitator when it comes to machine learning. Gupta explained that his company has been working on machine-learning algorithms for12 years, applying the technology to its flagship product.
Solido is confident of its technical chops. Its machine-learning technologies have been tested, proven in the company’s own commercial product (“Variation Designer,” launched in 2007), and backed by real-world users (1,000 designers and 35 major companies worldwide). Solido, says Gupta, already has seven lead customers committed to working at ML Labs and eager to put Solido’s expertise to use in other areas of EDA.
While declining to name names, Gupta indicated that Solido’s key clients range from a foundry to IDMs and fabless chip companies.
The idea of machine learning coming to chip design should come as no surprise, especially in the semiconductor industry. Major companies in the semiconductor ecosystem, foundries and EDA companies included, have been quietly investigating how best to apply machine learning to complex chip designs, development and testing to increase the efficiency and accuracy of both design and production.
Laurie Balch, chief analyst at Gary Smith EDA, acknowledged, “EDA tool companies are dabbling in [machine learning].” But she added, “I wouldn’t say they are doing it in such a vast way [throughout the EDA tool chain]. At least not yet.”
Partly, machine learning poses a tricky problem for EDA companies because they must deal with complex design data in vast variety. “To come up with good rules that produce repeatable results is a thorny issue,” said Balch.
Nonetheless, the idea of tapping artificial intelligence to improve design is picking up momentum.
Elyse Rosenbaum, director of the Center for Advanced Electronics through Machine Learning (CAEML), told EE Times earlier this year that CAEML’s AI project for electronics design has gained backing from the National Science Foundation and nine companies including Analog Devices, Cadence, Cisco, Hewlett-Packard Enterprise (HPE), IBM, Nvidia, Qualcomm, Samsung, and Xilinx.
Reached by EE Times and asked if CAEML is aware of Solido, Paul Franzon, professor of electrical and computer engineering at North Carolina State University, told us, “We know some of what our member companies are doing but Solido is not a member so we have not been tracking them at this point.”
Looking at Solido’s website, however, Franzon suspected what Solido does is “statistical in nature.” In his opinion, “Statistical analysis of ‘big data’ is a branch of machine learning that is fast growing in EDA, and there are many opportunities there.”
In contrast, he noted, CAEML’s main research focus has been in “building global models fitted to ‘training’ data produced by evaluation of the detailed model, or measurement of the detailed structure. These fast global models can then be used in design to get better designs faster.”
Solido’s Gupta, asked about CAEML’s efforts, said, “It’s great to see early ML research in EDA with an organization such as the CAEML.”
But he stressed that ML techniques are already starting to disrupt the EDA industry. “At Solido ML Labs, we are directly collaborating with lead customers to quickly develop and productize advanced Machine Learning products for EDA. We are leveraging the dozen years of proprietary and generally available ML R&D we applied to our products.”
Perhaps a better way to explain Solido’s ML efforts, compared to others, is that its software [i.e. Variation Designer] is much closer to manufacturing. As Gary Smith EDA’s Balch explained, “The focus of Solido’s software is on the implementation of designs, or getting their designs ready for production, in order to achieve higher accuracy and better yields.”
How it works
Solido’s key goals for its proprietary ML algorithms, Gupta explained, are threefold. They must result in “not estimation, but production accurate” products, they are “verifiable” and they offer “adaptive model building that is constantly improving.”
Obviously, they also need to be scalable. “When every transistor has eight to 10 process variables, we are talking about machine learning technologies that must scale to 100K+ input variables” to design a chip with 10k transistors, he added.
But how exactly do Solido’s ML technologies apply to the EDA flow?
First, users create specs for their own chips, and their variable input is fed into Solido’s ML algorithm. The SPICE simulator, driven by the ML algorithm, builds a model, which then predicts results.
This whole process is not done in a black box, stressed Gupta. Instead, the software offers a dashboard-like user interface, allowing designers to see and verify what it’s doing in real time.
If the system doesn’t see enough data to build a credible model, it will ask designers for more data. Designers might also switch to another software. But the idea is that the system is designed to build an adaptive model that self-verifies and corrects errors.
Without good tools, many chip designers tend to “over-design” or “under-design” chips, said Gupta. Or, they spend long hours “measuring variabilities and doing simulations.” To accelerate the process, designers can now resort to ML technologies. According to Solido, with its Variation Designer, designers can “reduce High-Sigma Monte Carlo from 5,000,000,000 simulations to 3,000 simulations.”
Speed isn’t the only objective. “Semiconductor designers are making very expensive decisions. Cost of making errors is very high,” said Gupta. This makes it absolutely critical for ML-enabled software to generate “production-accurate results,” he added.
Separately, Solido announced Thursday the release of its machine-learning characterization suite. The company said that the new product uses ML “to significantly reduce standard cell, memory, and I/O characterization time, helping semiconductor designers meet aggressive production schedules.”
The predictor that comes with Solido’s characterization suite can generate production-accurate library models at new corners, according to the company. It “reduces library characterization time by 30-70 percent,” which translates into savings on characterization licenses, simulation licenses, CPUs, disk and time, the company explained.
More work to do
It’s important to remember that the EDA community is a collection of niche players, noted Gary Smith EDA’s Balch, with each vendor attacking specific issues with specialized tools.
In a way, Solido is also a niche player working in specialized areas. Balch said this doesn’t detract from the fact that Solido is playing a key role with its own EDA piece. In her opinion, applying machine learning to chip designs in the EDA chain has barely begun.
Asked about the toughest areas — in chip designs — to apply ML algorithms, North Carolina State’s Franzon explained, “It’s not so much that certain problems can’t be cast this way [machine learning], but some are more difficult than others by their nature.”
He cited a few examples. One is “problems with too many dimensions,” he said. “Problems with 20+ dimensions are difficult to ‘fit’ or ‘train’ as you need too much data. We are investigating divide and conquer techniques to tackle these.”
Another is “Noisy data.” Franzon noted, “Some detailed models are ‘noisy,’ such as the same evaluation produces different results. We plan to look into ways to cope with this.”
Franzon also noted “difficulty producing the training set.” He explained, “Fitting a model requires hundreds of evaluation of the detailed model. Sometimes it’s hard to generate such a training data set.”
Meanwhile, Solido’s Gupta is hoping that his team’s ML technologies will be recognized as tools on which design engineers can bet their high-stakes chip designs.
— Junko Yoshida, Chief International Correspondent, EE Times